Next generation packaging technology for high performance ASICs

As the data rate of high performance Internet router systems continues to increase, meeting the challenges for high speed electrical performance drives ASIC packaging technology to higher silicon integration, higher I/O density, and enhanced thermal power dissipation. The requirement of high Si integration with the increasing needs for embedded SRAM and DRAM drives for the increase in Si die size and the demand for 90nm technology. Die size up to 20×20 mm is pushing advanced packaging substrate technology. High I/O density also drives the needs for finer bump pitch and larger package body size, which present challenges for package and card level assembly. Moreover, high availability telecommunication products demand excellent reliability not only at the ASIC package and card assembly level, but also at the final product system level.