Reusable design of run length coder for image compression application

Author

Park, SeongMo ; Park, Inhag ; Cha, Jinjong ; Cho, HanJin

Author_Institution

Micro-Electron. Tech. Lab., ETRI, Taejon, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

274

Lastpage

277

Abstract

In this paper, we describe the interface specification and core block design methods for a run length coder of video compression application. It offers high performance and many features to meet multimedia, and digital video applications. We designed the VLSI architecture of the run length coder using VHDL. This design can achieve a high performance for the video coder and is based on H.263 Recommendation. The format of the outputs is compatible with the stream of the variable length coding. The run length coder is implemented by the register transfer level (RTL) of VHDL. The designed block is synthesized by Compass synthesis with 0.5 μm CMOS, 3.3 V, technology and reuse as core IP (Intellectual Property) of H.263 and MPEG4 application. The run length coder block contains 4,000 logic gates and a total 1,536 bits of static RAM. The fully synchronous design allows for fast operation while maintaining a low gate count. The core will reuse for multimedia system and digital video applications

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; circuit CAD; data compression; digital signal processing chips; high level synthesis; image coding; multimedia systems; runlength codes; video coding; 0.5 micron; 3.3 V; CMOS technology; Compass synthesis; H.263 Recommendation; MPEG4 application; RTL; SRAM; VHDL; VLSI architecture; core IP; core block design methods; digital video applications; fully synchronous design; image compression application; interface specification; logic gates; multimedia applications; register transfer level; reusable design; run length coder; static RAM; variable length coding; video compression application; CMOS logic circuits; CMOS technology; Design methodology; Image coding; Intellectual property; Logic gates; MPEG 4 Standard; Streaming media; Very large scale integration; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824082

Filename

824082