Boundary scan design and verification flow using buffer chain method

Author

Chae, Eun-Seok ; Jun, Hong-Shin ; Song, Hye-Kyong

Author_Institution

Syst. LSI Div., Samsung Electron., Kyunki, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

303

Lastpage

306

Abstract

Boundary scan is a well-known standard DFT technique, called IEEE Std 1149.1, that is designed with boundary scan registers placed between pads and internal logic. In this paper we propose a boundary scan design and verification flow using a buffer chain method. The advantages of the proposed flow include: (1) the buffer chain method is easy to implement using the Samsung in-house tool; (2) the flow is effective in solving the post-layout problems at the pre-layout step; and (3) the flow reduces the TAT (Turn Around Time) of the boundary scan design and verification

Keywords

boundary scan testing; buffer circuits; circuit CAD; design for testability; formal verification; high level synthesis; integrated circuit design; integrated circuit testing; logic testing; CAD; DFT technique; IEEE Std 1149.1; Samsung in-house tool; boundary scan design; boundary scan registers; buffer chain method; verification flow; Circuit testing; Clocks; Computer aided engineering; Delay; Design for testability; Flip-flops; Large scale integration; Logic design; Printed circuits; Research and development;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824089

Filename

824089