DocumentCode
1641931
Title
A 32×32 self-timed multiplier with early completion
Author
Kim, Do-Wan ; Jeong, Deog-Kyoon
Author_Institution
Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
fYear
1999
fDate
6/21/1905 12:00:00 AM
Firstpage
319
Lastpage
322
Abstract
We designed a 32×32 self-timed multiplier with DCVSL. The multiplier supports both signed and unsigned integer multiplication, and adopts an early completion scheme for fast operation. We proposed a new 4-phase handshake circuit that fits well with DCVSL. We implement the proposed multiplier with 0.6 μm CMOS technology, and simulate the circuit with HSPICE. The latency of the multiplier is between 11.7 ns and 98.7 ns. The size of the core multiplier is about 1.8 mm×1.4 mm
Keywords
CMOS logic circuits; SPICE; circuit simulation; digital arithmetic; logic simulation; multiplying circuits; 0.6 micron; 11.7 to 98.7 ns; CMOS technology; DCVSL; HSPICE; core multiplier; early completion scheme; four-phase handshake circuit; latency; self-timed multiplier; signed integer multiplication; unsigned integer multiplication; CMOS technology; Circuit simulation; Clocks; Delay; Latches; Logic; Protocols; Robustness; Signal generators; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location
Seoul
Print_ISBN
0-7803-5705-1
Type
conf
DOI
10.1109/APASIC.1999.824093
Filename
824093
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