DocumentCode :
1642153
Title :
The implementation of the global scheduling strategy
Author :
Zhang, Jinyi ; Cai, Wanlin ; Wang, Chunhua
Author_Institution :
Key Lab. of Adv. Displays & Syst. Applic., Shanghai Univ., Shanghai, China
fYear :
2010
Firstpage :
1970
Lastpage :
1972
Abstract :
Today the research on design for testability is becoming the research priority in the filed of SoC. However, the traditional research is limited in top level of SoC and it ignores the inference resulting from the scheduling strategy in IP-core level. In addition, the work on stage of SoC overly focuses on researching the minimum testing time of different WSC. It ignores the relationship between the WSC and testing time. So the traditional research doesn´t play a significant role in design of SoC. In order to achieve the full use of testing resources, a bottom-up global scheduling strategy based on WSC balancing scan chain is proposed in this paper. In this paper, we verify the algorithm and reusability of this strategy upon the ITC´02 benchmark.
Keywords :
design for testability; integrated circuit design; integrated circuit testing; scheduling; system-on-chip; IP core level; ITC´02 benchmark; SoC; WSC balancing scan chain; design for testability; global scheduling strategy; Benchmark testing; Economics; IP networks; Optimization; Scheduling; System-on-a-chip; Balancing test chain; driftwood algorithm; global scheduling strategy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
Type :
conf
DOI :
10.1109/ICSICT.2010.5667834
Filename :
5667834
Link To Document :
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