Title :
A novel high-performance junctionless vertical MOSFET produced on bulk-Si wafer
Author :
Tai, Chih-Hsuan ; Lin, Jyi-Tsong ; Eng, Yi-Chuen ; Lin, Po-Hsieh
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
In this paper, we propose a junctionless vertical MOSFET (JLVMOS) based on bulk-Si wafer. According to the numerical simulations, the proposed JLVMOS can get a steep subthreshold swing (S. Swing), reduced DIBL, and higher ION/IOFF ratio, in comparison to a junctionless planar SOI MOSFET. This is because the vertical double-gate (DG) structure truly helps reduce the short-channel effects (SCEs). More importantly, SOI wafer is not necessary as a starting material for our proposed junctionless transistor, which is good for low-cost mass production.
Keywords :
MOSFET; elemental semiconductors; silicon; silicon-on-insulator; DG structure; DIBL; ION/IOFF ratio; JLVMOS; SCE; SOI wafer; bulk-silicon wafer; high-performance junctionless vertical MOSFET; junctionless planar SOI MOSFET; junctionless transistor; low-cost mass production; short-channel effects; steep subthreshold swing; vertical double-gate structure; Logic gates; MOSFET circuits; Numerical simulation; Performance evaluation; Silicon; Transistors;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667835
