Title :
A low-offset dynamic comparator using bulk biasing technique in digital 65nm CMOS technology
Author :
Xu, Ye ; Ytterdal, Trond
Author_Institution :
Dept. of Electron. & Telecommun., Norwegian Univ. of Sci. & Technol., Trondheim, Norway
Abstract :
This paper presents a low-offset, low-power, high-speed comparator using bulk biasing calibration technique. The adjustment of bulk voltage is realized by analog integration in a feedback loop. The technique can calibrate the offset voltage to small value without reducing speed. The comparator is designed in a standard digital 65nm CMOS technology with 1V supply voltage. The comparator works at 1GHz clock frequency. Simulation results show that it achieves 1.2 mV offset voltage and 1.1mV input referred RMS noise, while dissipating 14fJ/comparison.
Keywords :
CMOS digital integrated circuits; comparators (circuits); feedback; CMOS technology; RMS noise; bulk biasing calibration technique; clock frequency; feedback loop; frequency 1 GHz; high-speed comparator; low-offset dynamic comparator; size 65 nm; voltage 1 V; voltage 1.1 mV; voltage 1.2 mV; CMOS integrated circuits; CMOS technology; Calibration; Delay; Noise; Simulation; Transistors;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667838
