Automated test bitstream generation for an SOI-based FPGA

In this paper, we propose a methodology of the automated bitstream generation for conducting high-testability FPGA tests. In order to study the efficiency of our solution we will explore our methodology in the test of an SOI-based FPGA. We use a semi-automated approach of the bitstream generation for ease of test vector design with high functionality and fault coverage. The methodology from this research is extensively exercised in the design process. The quality of this methodology is proven by the efficiency of the test vector suite used in the wafer and packaged tests. The same approach can also be used in the bitstream generation for FPGA application.