Use-dependent delay analysis of synchronous circuits

Exhaustive data-dependent simulation is expensive and can exercise impossible streams of transitions that could not occur during a circuit´s actual use. An investigation of the speed of a circuit may therefore find the slowest path to be one that could not occur in practice. In such a case, the estimate of the worst-case delay through the circuit would be pessimistic. A system is described which overcomes these problems by performing simulation in the context of a circuit´s intended use. The technique also facilitates much pruning of the simulation. The author describes a second and complementary technique that can prune the simulation further at the gate level without affecting the predicted delay and critical path of synchronous circuits. An application of these techniques to synchronous state machines is described