The design and implement of a mobile security SoC

Author

Huang, Wei ; Han, Jun ; Wang, Shuai ; Zeng, Xiaoyang

Author_Institution

State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2010

Firstpage

96

Lastpage

98

Abstract

This paper presents a mobile security SoC to deal with intensive cryptography algorithms for different security protocols. A MIPS-like general processor, a dedicated package processor for fast data package, and multiple security processors for cryptography are integrated in the SoC. Moreover, the performance can be greatly enhanced by the well-designed DTU (Data Transfer Unit), memory architecture and synchronization units. With the help of our MIPS, software of the processors could be programmed flexibly to fulfill the requirements of the different security protocols. A test chip is implemented in SMIC 0.13μm standard CMOS technology, and its functionality and performance are well verified. It can achieve 565Mbps, 256Mbps, 19Kbps and 16Kbps throughput for AES (128), SHA-1, RSA (1024), ECC (192) respectively.

Keywords

CMOS digital integrated circuits; cryptographic protocols; system-on-chip; AES; ECC; MlPS-like general processor; SHA-1; SMIC standard CMOS technology; bit rate 16 kbit/s; bit rate 19 kbit/s; bit rate 256 Mbit/s; bit rate 565 Mbit/s; data transfer unit; fast data package; intensive cryptography algorithms; memory architecture; mobile security SoC; multiple security processors; package processor; security protocols; size 0.13 mum; synchronization units; Algorithm design and analysis; Computer architecture; Cryptography; Protocols; Random access memory; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667841

Filename

5667841