Advanced technology for FPGAs

Author

Xiang, Qi

Author_Institution

Altera Corp., San Jose, CA, USA

fYear

2010

Firstpage

58

Lastpage

61

Abstract

Power management and high speed transceiver I/O demands are two major challenges for advanced field programmable gate array (FPGA) at 28nm node. To meet requirements, not only innovations in process technology but also co-optimization of process, circuit and system architecture are required. Advanced process technologies, such as high-k metal gate (HKMG) and enhanced strain engineering, significantly improves performance while reducing leakage power. With co-optimization of process, circuit, and architecture, 30% lower total power is achieved for 28nm FPGAs vs. previous generations. With optimized analog/RF devices, high data rate of 28 Gbps transceivers are produced using a 28nm digital process.

Keywords

electrical faults; field programmable gate arrays; transceivers; FPGA; I/O demands; analog/RF devices; co-optimization; high speed transceiver; high-k metal gate; leakage power; power management; size 28 nm; strain engineering; Field programmable gate arrays; Logic gates; Performance evaluation; Radio frequency; Strain; Transceivers; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667854

Filename

5667854