A novel thyristor-based SRAM cell (T-RAM) for high-speed, low-voltage, giga-scale memories

Author

Nemati, F. ; Plummer, J.D.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1999

Firstpage

283

Lastpage

286

Abstract

T-RAM is a novel high-density SRAM cell based on a vertical surrounding-gate thyristor with a novel gate-assisted switching mechanism. In this paper, the first experimental integration of the vertical surrounding-gate thyristors and planar NMOS-FETs to make T-RAM cells is reported. Our measurements on various device geometries confirm a standby current below 10 pA for T-RAM in a 0.5 /spl mu/m or smaller technology and a speed of 5 ns. It is also shown that the performance of a T-RAM cell improves with the down-scaling of the thickness of the thyristors. The thermal stability of a T-RAM cell is also investigated.

Keywords

SRAM chips; high-speed integrated circuits; low-power electronics; negative resistance circuits; thyristors; 0.5 micron; 10 pA; 5 ns; SRAM; T-RAM; gate-assisted switching; high-speed low-voltage memory cell; negative differential resistance; planar NMOSFET; standby current; thermal stability; vertical surrounding-gate thyristor; Current measurement; Etching; FETs; Fabrication; MOSFET circuits; Random access memory; Read-write memory; Switches; Thyristors; Velocity measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-5410-9

Type

conf

DOI

10.1109/IEDM.1999.824152

Filename

824152