DocumentCode
1643103
Title
Predictive BSIM3v3 modeling for the 0.15-0.18 /spl mu/m CMOS technology node: a process DOE based approach
Author
Vasanth, K. ; Krick, J. ; Unnikrishnan, S. ; Nandakumar, M. ; Jacobs, J. ; Ehnis, P. ; Green, K. ; Machala, C. ; Vrotsos, T.
Author_Institution
Spice Modeling Lab., Texas Instrum. Inc., Dallas, TX, USA
fYear
1999
Firstpage
353
Lastpage
356
Abstract
An efficient and accurate approach using the BSIM3v3 compact model to support concurrent process technology development and circuit design is presented. The key feature is the ability to generate accurate pre-silicon BSIM3 models for new technologies taking into account process information from existing technologies. Device, circuit and process optimization results are presented.
Keywords
CMOS integrated circuits; design of experiments; integrated circuit technology; semiconductor process modelling; 0.15 to 0.18 micron; BSIM3v3 model; CMOS technology; circuit design; design of experiments; process optimization; CMOS process; CMOS technology; Calibration; Circuit simulation; Data mining; Parameter extraction; Predictive models; Semiconductor device modeling; Space technology; US Department of Energy;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location
Washington, DC, USA
Print_ISBN
0-7803-5410-9
Type
conf
DOI
10.1109/IEDM.1999.824168
Filename
824168
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