Title :
Mobility enhancement in silicon nanowire transistors
Author :
Hiramoto, Toshiro ; Chen, Jiezhi ; Saraya, Takuya
Author_Institution :
Inst. of Ind. Sci., Univ. of Tokyo, Tokyo, Japan
Abstract :
Electron and hole mobility in sub-10nm silicon nanowire FETs on (100) SOI has been systematically investigated experimentally. The nanowire height of fabricated nanowire FETs is as low as 4 - 10nm and the minimum nanowire width is shrunk to 5nm. Higher hole mobility than (100) universal mobility is experimentally observed for the first time in 9nm-wide nanowire and even in 5nm-wide nanowire, while electron mobility degradation is minimized in nanowire nFET. Underlying physical mechanisms are discussed.
Keywords :
electron mobility; field effect transistors; hole mobility; nanowires; silicon; silicon-on-insulator; SOI; Si; electron mobility degradation; fabricated nanowire FET; hole mobility; mobility enhancement; nanowire nFET; silicon nanowire FET; silicon nanowire transistors; size 9 mm; universal mobility; Degradation; Electron mobility; FETs; Logic gates; Scattering; Silicon;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667872
