CSLC: The infrastructure compiler for SoC design

The paper presents a new high level design tool and methodology that are used to accelerate the design process. The high level design tool named CSLC starts with a description of interfaces, hierarchies and connections generating a design and verification infrastructure composed of interconnect, hierarchy, test benches, a high level simulation model, verification vectors and documentation. Design specification is based on Chip Specification Language (CSL) and brings significant reduction in setup and maintenance of complex designs. The fundamental idea that CSL is based on is that there is a single source for all derived design, verification, and high level simulation objects.