DocumentCode
1643351
Title
A BS-BIST test circuit design for VAD-SOC
Author
Jianfeng, Li ; Jinyi, Zhang ; Jiao, Li ; Laijin, Yan
Author_Institution
Microelectron. R&D Center, Shanghai Univ., China
fYear
2004
Firstpage
385
Lastpage
389
Abstract
Along with the more complicated integrated circuit system and the emergence of intelligent properties (IP-based) system on a chip (SOC) system, the test of IC system becomes more difficult and faces new challenge. In this paper we design a BS-BIST test circuit after studying built in self test (BIST) and boundary-scan (BS) technique respectively. At the base of increasing little of cost in circuit complexity, it combines video add data (VAD) SOC to overcome many problems in the test of IP-based SOC system.
Keywords
boundary scan testing; built-in self test; circuit complexity; integrated circuit testing; system-on-chip; BS-BIST test circuit design; VAD-SOC; boundary-san technique; built in self test; circuit complexity; integrated circuit system; intelligent properties; system on chip system; video add data SOC; Automatic testing; Built-in self-test; Circuit synthesis; Circuit testing; Complexity theory; Costs; Integrated circuit testing; Intelligent systems; System testing; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
High Density Microsystem Design and Packaging and Component Failure Analysis, 2004. HDP '04. Proceeding of the Sixth IEEE CPMT Conference on
Print_ISBN
0-7803-8620-5
Type
conf
DOI
10.1109/HPD.2004.1346735
Filename
1346735
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