DocumentCode
1643364
Title
Design and implementation of RS(255,223) decoder on FPGA
Author
Laijin, Yan ; Ming, Li
Author_Institution
Microelectron. Res. & Developing Center, Shanghai Univ., China
fYear
2004
Firstpage
390
Lastpage
393
Abstract
This paper proposes a RS(255,223) decoder for applications that require high-speed data communication and reliability. The proposed architecture employs a modified Euclidean algorithm, the Chien search and Forney´s algorithm using parallel processing technology. The complexity of this decoder is about 130,000 gates; the total latency is 560 cycles; and the throughput is 180Mbps under 20MHz. Comparing with similar designs, this design has smaller latency, moderate area, and high throughput rate.
Keywords
data communication equipment; decoding; field programmable gate arrays; Chien search; Euclidean algorithm; FPGA; Forney algorithm; RS(255,223) decoder; high-speed data communication; parallel processing technology; Block codes; Decoding; Delay; Error correction; Field programmable gate arrays; Galois fields; Hardware design languages; Polynomials; Reed-Solomon codes; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
High Density Microsystem Design and Packaging and Component Failure Analysis, 2004. HDP '04. Proceeding of the Sixth IEEE CPMT Conference on
Print_ISBN
0-7803-8620-5
Type
conf
DOI
10.1109/HPD.2004.1346736
Filename
1346736
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