DocumentCode
1643542
Title
Dual-path frequency compensation for current-mode buck converters
Author
Pang-Jung Liu ; Shang-Ru Hsu ; Tzu-Hsuan Chen
Author_Institution
Dept. of Electr. Eng., Nat. Taipei Univ. of Technol., Taipei, Taiwan
fYear
2015
Firstpage
432
Lastpage
436
Abstract
This paper proposes a dual-path frequency compensation (DPFC) for implementing on-chip error amplifier (EA). The DPFC uses two operation amplifiers to simultaneously charge and discharge a compensation capacitor. As a result, the equivalent capacitance is significantly multiplied with small additional power and silicon area. Since the slew rate of the EA is increased owing to the small compensation capacitance, the transient response of the buck converter is also enhanced dramatically. A laboratory converter with the DPFC is implemented with 0.35-μm CMOS process. Simulation results demonstrate the converter stability and transient response. The transient recovery time is less than 4 μs for load current changing from 500 mA to 50 mA. With the DPFC, the compensation capacitor is shrunk significantly and no compensation resistor is needed.
Keywords
CMOS integrated circuits; capacitors; error compensation; operational amplifiers; power convertors; CMOS process; DPFC; EA slew rate; current-mode buck converter; dual-path frequency compensation; on-chip error operational amplifier; size 0.35 mum; transient recovery time; transient response; Capacitance; Capacitors; DC-DC power converters; Frequency conversion; Simulation; System-on-chip; Transient response; Frequency compensation; dc-dc converter; slew rat; transient response;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Electronics and Drive Systems (PEDS), 2015 IEEE 11th International Conference on
Conference_Location
Sydney, NSW
Type
conf
DOI
10.1109/PEDS.2015.7203519
Filename
7203519
Link To Document