Design and implementation of flash ADC and DBNS FIR filter

Digital signal processing (DSP) system has been widely used in telecommunication, audio, video, avionics, bio-medical instruments, and portable electronic products. However, DSP needs fast multipliers and adders to process signals at real time. The double base number system (DBNS) can process arithmetic operation fast due to the multidimensional logarithmic number feature, which is suitable for multiplier accumulator architecture of DSP. This system can reduce the hardware complexity by inner product operation. This paper uses the DBNS to improve the DSP arithmetic operation speed with the flash ADC. A 6-bit flash ADC is designed with the 0.18 ¿m CMOS technology. The HSPICE simulation of proposed coding technique shows 11% and 100% improvement in speed compared with FAT tree encoder and ROM based encoder respectively. In addition, the circuit saved up to 8.16% and 174.85% in power consumption.