Experimental examination of physical model for direct tunneling current in unstressed/stressed ultrathin gate oxides

Physical mechanism of direct tunneling in unstressed and stressed gate oxides thinner than 5 nm is experimentally investigated. It is revealed that the direct tunneling current in an unstressed MOS (n/sup +/-poly Si/SiO/sub 2//Si substrates) structure has a strong bias polarity dependence, which is determined through the competing effects of tunneling probability and the number of tunneling carriers. It is also found that a leakage path allowing the flow of holes dominates SILC and leakage current after soft breakdown in stressed oxides less than 5 nm. This leakage path has the asymmetric carrier conduction property that current from the Si substrate is much larger than that from the n/sup +/-poly gate.