DocumentCode
1643906
Title
Loop closure variation windows: Linking manufacturing and design
Author
Gu, Cong ; Chen, Hong ; Li, Lisheng ; Bates, John
Author_Institution
TSO Design Enable Group, Freescale Semicond. Ltd., Beijing, China
fYear
2010
Firstpage
2022
Lastpage
2024
Abstract
The paper presents loop closure methodology to disclose the variation window of fab for a technology to robust design for manufacturability. With automatically screened fab raw data, the clean data is collected for many months allowing good prediction of future results for overall fab capability and also used for monitoring fab performance versus design libraries and technology specs to ensure that design libraries match the actual production capability. Multiple formats of viewing data accelerate debug of problems and also useful for fab yield enhancement, product debug, and model casing alignments etc.
Keywords
design for manufacture; integrated circuit design; integrated circuit manufacture; semiconductor technology; data accelerate debug; design; loop closure variation windows; manufacturability; Data models; Databases; Integrated circuit modeling; Libraries; Manufacturing; Solid modeling; SPICE; circuit simulation; closed loop; modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location
Shanghai
Print_ISBN
978-1-4244-5797-7
Type
conf
DOI
10.1109/ICSICT.2010.5667894
Filename
5667894
Link To Document