Thermal analysis on a two chip TSS

3D ICs is a new technology for achieving high density, low power and cost effective designs. As a result of dies being stacked over each other, TSS (Through Silicon tsv Stack) poses a challenge of heat flow and temperature management. A die level thermal analysis tool which can analyze a stacked die configuration, modeling boundary conditions, TSVs and fit into existing SoC design flows is the need of hour for 3D IC designers. In this paper, a thermal tool of Cadence which meets the requirement exactly is introduced. We present a flow for 3D thermal analysis of a two chip TSS (Through Silicon tsv Stack) design and also present the results of experiments done to validate the flow. Special acknowledge to Mark Nakamoto, Radojcic Riko and Bai Cher at Qualcomm.