A switched-current third-order oversampling modulator with coupled differential replica FMC

This paper presents a switched-current (SI) third-order sigma-delta modulator (SDM) which consists of a current-mode sample-and-hold (S/H) and a feedback topology to reduce the input impedance at input terminal, and a common-mode feed-forward (CMFF) circuit to improve the common-mode offset at output terminal. Besides, a SI feedback memory cell (FMC) with low clock feedthrough (CFT) error is presented with a coupled differential replica (CDR) topology. The proposed third-order SDM is designed and implemented with standard 0.35-μm CMOS technology. The simulation results show that the peak value of signal to noise plus distortion ratio (SNDR) is roughly 104.9 dB at the sampling rate of 10.24 MHz and the signal bandwidth of 80 kHz. However, the power dissipation of 33 mW is too large at power supply voltage of 2.5 V.