Discrete-time cellular neural networks using digital neuron model with DPLL

Author

Ueda, Toshitsugu ; Takahashi, Kiyoshi ; Ho, Chun-ying ; Mori, Shinsaku

Author_Institution

Dept. of Electr. Eng., Keio Univ., Yokohama, Japan

fYear

1992

Firstpage

252

Lastpage

257

Abstract

Discrete-time cellular neural networks using a digital neuron model with DPLL (digital phase-locked loop) are proposed. Since the model consists of all digital elements, it is easy to realize it by VLSI. The model is theoretically analyzed and applied to the shadow detector of H. Harrer and J.A. Nossek (IEEE Int. Joint Conf. on Neural Networks-Sin 718-22, 1991). The analysis confirms the computer simulation of the neuron model

Keywords

VLSI; cellular arrays; neural chips; phase-locked loops; CNN; DPLL; VLSI; digital phase-locked loop; discrete-time cellular neural networks; Analog circuits; Cellular networks; Cellular neural networks; Computer simulation; Detectors; Digital filters; Electronic mail; Neurons; Phase modulation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Cellular Neural Networks and their Applications, 1992. CNNA-92 Proceedings., Second International Workshop on

Conference_Location

Munich

Print_ISBN

0-7803-0875-1

Type

conf

DOI

10.1109/CNNA.1992.274360

Filename

274360

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1644118