MOS translinear principle based analog four-quadrant multiplier

This paper presents a MOS translinear principle based current mode CMOS four-quadrant multiplier. The multiplication is implemented by two MOS translinear loops working in the subthreshold region. The remainder of the differential output currents is the multiplication of the signals carried by the differential input currents. The multiplier characterized with a high bandwidth and low power consumption. The simulation results show a THD lower than 3.0% in 1MHz, a -3dB bandwidth of more than 58MHz and the maximum power consumption is 60μW. However, the body effect of NMOS transistors in CMOS process will introduce great nonlinearity error. Fortunately, the body effect can be eliminated by modifying the multiplier topology with PMOS transistors for applications using standard CMOS process. Simulation results using a 0.5μm BCD process are presented and discussed.