Title :
Statistical pn junction leakage model with trap level fluctuation for Tref (refresh time)-oriented DRAM design
Author :
Kamohara, S. ; Kubota, K. ; Moniwa, M. ; Ohyu, K. ; Ogishima, A.
Author_Institution :
Semicond. & Integrated Circuits Div., Hitachi Ltd., Tokyo, Japan
Abstract :
By analyzing the anomalous junction leakage of a single tail bit and introducing the trap level fluctuation model, we have successfully established a methodology for predicting the refresh time (Tref) of the current and next generations for the Tref-oriented DRAM design optimization.
Keywords :
DRAM chips; electron traps; integrated circuit design; integrated circuit modelling; leakage currents; p-n junctions; semiconductor device models; DRAM design optimization; anomalous junction leakage; effective band gap; refresh time-oriented DRAM design; single tail bit; statistical pn junction leakage model; storage capacitance; trap level fluctuation; Design optimization; Fluctuations; Integrated circuit modeling; Leakage current; Predictive models; Probability distribution; Random access memory; Substrates; Tail; Transistors;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824211
