Design optimization of adjustable triggering dual-polarity ESD protection structures

Author

Liu, Jian ; Lin, L. ; Wang, X. ; Shi, Z. ; Fan, S. ; Tang, H. ; Wang, A. ; Cheng, Y. ; Zhao, B.

Author_Institution

Dept. of Electr. Eng., Univ. of California, Riverside, CA, USA

fYear

2010

Firstpage

149

Lastpage

152

Abstract

We report design optimization of new low-triggering dual-directional SCR (LTdSCR) ESD protection structures in BiCMOS. Design optimization techniques to adjust ESD triggering voltage (V_t1), as well as its impacts on ESD holding voltage (V_h) and ESD protection capability, are discussed. Measurements show very low and adjustable V_t1, low leakage (I_leak), low noise figure (NF), low ESD-induced parasitic capacitance (C_ESD) and fast ESD triggering time (t₁). High ESD protection to Si ratio of ESDV~7.49V/μm² is achieved.

Keywords

BiCMOS integrated circuits; circuit optimisation; electrostatic discharge; integrated circuit design; thyristors; BiCMOS; ESD holding voltage; ESD protection capability; ESD triggering time; ESD triggering voltage; ESD-induced parasitic capacitance; adjustable triggering dual-polarity ESD protection structures; design optimization; low-triggering dual-directional SCR; noise figure; BiCMOS integrated circuits; Design optimization; Electrostatic discharge; Noise measurement; Testing; Thyristors; ESD protection; RF; SCR; adjustable triggering; dual-polarity;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2010 IEEE

Conference_Location

Austin, TX

ISSN

1088-9299

Print_ISBN

978-1-4244-8578-9

Type

conf

DOI

10.1109/BIPOL.2010.5667913

Filename

5667913