Title :
Design optimization of adjustable triggering dual-polarity ESD protection structures
Author :
Liu, Jian ; Lin, L. ; Wang, X. ; Shi, Z. ; Fan, S. ; Tang, H. ; Wang, A. ; Cheng, Y. ; Zhao, B.
Author_Institution :
Dept. of Electr. Eng., Univ. of California, Riverside, CA, USA
Abstract :
We report design optimization of new low-triggering dual-directional SCR (LTdSCR) ESD protection structures in BiCMOS. Design optimization techniques to adjust ESD triggering voltage (Vt1), as well as its impacts on ESD holding voltage (Vh) and ESD protection capability, are discussed. Measurements show very low and adjustable Vt1, low leakage (Ileak), low noise figure (NF), low ESD-induced parasitic capacitance (CESD) and fast ESD triggering time (t1). High ESD protection to Si ratio of ESDV~7.49V/μm2 is achieved.
Keywords :
BiCMOS integrated circuits; circuit optimisation; electrostatic discharge; integrated circuit design; thyristors; BiCMOS; ESD holding voltage; ESD protection capability; ESD triggering time; ESD triggering voltage; ESD-induced parasitic capacitance; adjustable triggering dual-polarity ESD protection structures; design optimization; low-triggering dual-directional SCR; noise figure; BiCMOS integrated circuits; Design optimization; Electrostatic discharge; Noise measurement; Testing; Thyristors; ESD protection; RF; SCR; adjustable triggering; dual-polarity;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2010 IEEE
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-8578-9
DOI :
10.1109/BIPOL.2010.5667913
