Sequential test generation based on real-valued logic simulation

This work presents an approach to the test generation for synchronous sequential circuits. This approach utilizes an extended logic simulation, called real-valued logic simulation, and solves the sequential test generation problem as a kind of optimization problem. The approach has the possibility of high speed test generation, because high speed processing techniques, such as, vector processing, parallel processing, and so on, can be efficiently applied to the most time-consuming part of this approach. Experimental results for ISCAS´89 benchmark sequential circuits also illustrate the eficiency of this approach.