Title :
Design of low-jitter clock duty cycle stabilizer in high-performance pipelined ADC
Author :
Zhang, Mingwen ; Yin, Yongsheng ; Deng, Honghui ; Chen, Hongmei
Author_Institution :
Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China
Abstract :
This paper introduces a design of clock duty cycle stabilizer (DCS) for high-speed pipelined ADC, and analyses the internal parameters on the impact of the circuit performance. Circuit module includes programmable clock input buffer, clock synthesizer, duty cycle detection circuit and nonoverlapping clock generation circuit. The circuit and layout are achieved by 0.18 μm CMOS 1P5M Mixed Signal process. The Cadence Spectre post-simulation results show: The circuit can work for a wide frequency range from 20MHz to 250MHz; duty cycle accuracy of (50±0.25) %, in the 250MHz input frequency, the RMS jitter is 53 fs. The measured performance shows it can work with high speed, high precision and low jitter characteristics, being not strictly requirement on the input clock signal, nonoverlapping time controllable.
Keywords :
CMOS integrated circuits; analogue-digital conversion; clocks; integrated circuit design; jitter; CMOS 1P5M mixed signal process; Cadence Spectre; RMS jitter; circuit module; circuit performance; clock synthesizer; duty cycle detection circuit; high-performance pipelined ADC; high-speed pipelined ADC; input clock signal; low jitter characteristics; low-jitter clock duty cycle stabilizer; nonoverlapping clock generation circuit; programmable clock input buffer; Clocks; Delay; Image edge detection; Jitter; Noise; Operational amplifiers; Voltage control; 50% duty cycle; clock jitter; high-performance pipelined ADC; nonoverlapping clock; the duty cycle detector;
Conference_Titel :
Anti-Counterfeiting, Security and Identification (ASID), 2012 International Conference on
Conference_Location :
Taipei
Print_ISBN :
978-1-4673-2144-0
Electronic_ISBN :
2163-5048
DOI :
10.1109/ICASID.2012.6325310