Title :
An Advanced BIRA using parallel sub-analyzers for embedded memories
Author :
Jeong, Woosik ; Han, Taewoo ; Kang, Sungho
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
Abstract :
Although many built-in redundancy analysis (BIRA) algorithms which use parallel sub-analyzers have optimal repair rate and a fast analysis speed, they suffer from a large area overhead. To reduce the area overhead, a new BIRA analyzer is proposed which reconstructs the content addressable memory (CAM) structure of the parallel sub-analyzers like a binary searching tree. Experimental results show that the proposed BIRA analyzer achieves 25% reduction of area overhead compared with previous BIRA using parallel sub-analyzers in case an embedded memory has 4 spares with optimal repair rate and zero analysis speed.
Keywords :
content-addressable storage; embedded systems; parallel algorithms; system-on-chip; advanced BIRA; binary searching tree; built-in redundancy analysis algorithms; content addressable memory structure; embedded memories; parallel subanalyzers; systems-on-chip; Algorithm design and analysis; Associative memory; CADCAM; Capacity planning; Computer aided manufacturing; Electrostatic precipitators; Fault detection; Logic; Redundancy; Silicon; area overhead; built-in self repair (BISR); embedded memory; optimal repair; redundancy anlaysis (RA);
Conference_Titel :
SoC Design Conference (ISOCC), 2009 International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-5034-3
Electronic_ISBN :
978-1-4244-5035-0
DOI :
10.1109/SOCDC.2009.5423810
