DocumentCode
1644376
Title
Self-retention of data in power-gated circuits
Author
Seomun, Jun ; Shin, Youngsoo
Author_Institution
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
fYear
2009
Firstpage
212
Lastpage
215
Abstract
Data retention is important to avoid data loss in power-gated circuits. Isolation circuitry should be used to keep output value as well as to avoid floating; a flip-flop capable of data retention, called retention flip-flop, should be used to keep flip-flop state. Examples of their implementations are reviewed. Due to extra circuitry and wires they introduce, it is important to understand how much increase of area and wirelength should be tolerated to support data retention, which we quantitatively analyze using several example circuits in 65-nm technology. A self-retention mechanism is proposed to alleviate the increase; it relies on the potential change of virtual power rail to detect the time for data retention and data restore thereby removing control signal implemented as extra wires and buffers in conventional power-gated circuits. Experiments show 8.6% decrease of wires on average.
Keywords
flip-flops; logic design; data self-retention; isolation circuit; power-gated circuits; retention flip-flop; size 65 nm; Flip-flops; Inverters; Isolators; MOS devices; Rails; Signal restoration; Switches; Switching circuits; Variable structure systems; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2009 International
Conference_Location
Busan
Print_ISBN
978-1-4244-5034-3
Electronic_ISBN
978-1-4244-5035-0
Type
conf
DOI
10.1109/SOCDC.2009.5423812
Filename
5423812
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