Design and testing issues in current-mode cellular neural networks

A general technique for continuous time (CT) and discrete time (DT) cellular neural network (CNN) implementation using current-mode techniques is presented. The proposed methodology yields high pixel densities, high speed, and low power consumption, while the design procedure is extremely simple. The resulting circuits are well suited for standard digital CMOS processes, since only MOS transistors are required. CNN cell layouts are shown together with electrical simulation results from extracted netlists of complete networks. Monte Carlo analysis demonstrates the viability of the proposed techniques. Basic building blocks have been experimentally tested