SOC power off - power noise analysis

Advancing to sub-micron processes, power gating using MTCMOS has been widely adopted in complex SOC to reduce the leakage current. Increasing computing applications especially mobile and wireless chip designs require extensive power gating design to power on and off modules in designs. The power signature goes hand-in-hand with the end-product usage model. Even though power gating helps to reduce the leakage, it generates significant power noise which affects chip functional stability. This paper focuses on the analysis of power noise caused by power off operation. It describes the noise coupling at both the system and the die levels in section II. The power-off circuit modeling will be explained in section III. A comparison of silicon measurement result to spice simulation as well as a prominent power noise EDA tool are presented in section IV.