DocumentCode
1644429
Title
A gate delay model considering temporal proximity of Multiple Input Switching
Author
Shin, Janghyuk ; Kim, Juho ; Jang, Naeun ; Park, Eunsuk ; Choi, Yangmin
Author_Institution
Dept. of Comput. Sci. & Eng., Sogang Univ., Seoul, South Korea
fYear
2009
Firstpage
577
Lastpage
580
Abstract
Conventional cell characterization does not consider multiple input switching (MIS). Since the impact of MIS on gate delay variation is large, it is not possible to predict the accurate gate delay with the conventional cell characterization. We observed maximum 46% difference in gate delay due to MIS. In this paper, we propose a gate delay model considering the delay variation caused by temporal proximity of MIS. The proposed model calculates the delay variation using the radial basis function (RBF). The experimental results show that the proposed method can more accurately predict gate delay when MIS occurs.
Keywords
delay circuits; integrated circuit modelling; radial basis function networks; accurate gate delay; delay variation; gate delay model; multiple input switching; radial basis function; temporal proximity; Capacitance; Circuit analysis; Clocks; Computer science; Delay effects; Delay estimation; Frequency; Libraries; MOSFETs; Timing; cell characterization; delay model; multiple input switching; proximity; temporal;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2009 International
Conference_Location
Busan
Print_ISBN
978-1-4244-5034-3
Electronic_ISBN
978-1-4244-5035-0
Type
conf
DOI
10.1109/SOCDC.2009.5423815
Filename
5423815
Link To Document