Low-complexity folded FIR filter architecture for ATSC DTV tuner

This paper presents an efficient folded finite-impulse response (FIR) filters for digital TV tuner. DTV receivers are widely used in many electronic systems such as HD-TV, set-top box, PDA and cell phones. The DTV tuner that is a major power expender and costly device in the receiver selects the desired signals from many signals available and down-converts them. To reduce hardware complexity, the folded architectures are proposed and common subexpression elimination (CSE) methods based on binary representation of coefficients for the high order FIR filters are used in this paper. The implementation result show that proposed folded FIR filter operates at a clock frequency of 200 MHz and has 60% less hardware complexity than unfolded structure for 90-nm CMOS technology. Also, the proposed folded architecture has 12% less complexity than the other folded architecture.