Inter-hierarchical power analysis methodology to reduce multiple orders of magnitude run-time without compromizing accuracy

Now, it is very common to require more than ten engineering-change-order (ECO) iterations to sign-off VLSI design in scaled technologies because engineers should close not only circuit speed, but also power. One of the main components of the long turn-around-time for closing power is generating activity files at gate level or at register-transfer-level (RTL) to analyze the power. This paper describes a method to reduce the power-analysis run time multiple orders of magnitude maintaining gate-level power-analysis accuracy. To reduce the run-time dramatically for power analysis, novel activity-propagation and port-mapping algorithms to convert automatically from electronic-system-level (ESL) activity file to RTL vcd (value change dump) file and to gate-level vcd file have been proposed. After obtaining all vcd files in each level, we can do power analysis without accuracy degradation at RTL and at gate level. In this method, a huge amount of run time for simulation in each level is reduced. By analyzing a variety of digital circuits, we demonstrate the run-time of our methodology is an order of magnitude faster than traditional method at RTL and multiple orders of magnitude faster at gate level with less than 1% accuracy degradation of RTL and gate-level power analysis.