Title :
0.5-/spl mu/m-pitch copper-dual-damascene metallization using organic SOG (k=2.9) for 0.18-/spl mu/m CMOS applications
Author :
Fukuda, T. ; Ohshima, T. ; Aoki, H. ; Maruyama, H. ; Miyazaki, H. ; Konishi, N. ; Fukada, S. ; Yunogami, T. ; Hotta, S. ; Maekawa, A. ; Hinode, K. ; Nojiri, Kousei ; Tokunaga, T. ; Kobayashi, N.
Author_Institution :
Device Dev. Center, Hitachi Ltd., Japan
Abstract :
We developed 0.5 /spl mu/m-pitch Cu-dual-damascene metallization by using very low-k organic SOG (HSG-R7; Hitachi Chemical Co., k=2.9) as the ILD. Interconnects using HSG reduced the interconnect capacitance by 30% compared to that of interconnects using TEOS. Furthermore, the electrical characteristics, such as line and via resistances, show that the HSG-ILD combination is feasible for 0.18-/spl mu/m CMOS applications.
Keywords :
CMOS integrated circuits; capacitance; copper; delays; dielectric thin films; etching; integrated circuit interconnections; integrated circuit metallisation; organic compounds; 0.18 mum; 0.5 /spl mu/m-pitch Cu dual-damascene metallization; 0.5 mum; CMOS applications; Cu; HSG-ILD combination; HSG-R7; RC delay time; electrical characteristics; interconnect capacitance; line resistance; organic SOG; process integration; selective etching; very low-k organic ILD; via resistance; Conductive films; Delay effects; Etching; Logic devices; Metallization; Plasma applications; Plasma properties; Plasma stability; Plasma temperature; Tin;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824229
