DocumentCode
1644676
Title
Design verification of a high density computer using IEEE 1149.1
Author
Daniel, Wayne T.
fYear
1995
Firstpage
84
Lastpage
90
Abstract
This paper discusses the use of the IEEE 1149.1 test bus, internal scan and built-in emulation logic in the design verification and system integration of an embedded 100Mhz high density scalarlvector parallel processing computer.
Keywords
Application specific integrated circuits; Concurrent computing; Embedded computing; Emulation; Logic design; Logic devices; Logic testing; Military computing; Software testing; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1992. Proceedings., International
Conference_Location
Baltimore, MD
ISSN
1089-3539
Print_ISBN
0-7803-0760-7
Type
conf
DOI
10.1109/TEST.1992.527807
Filename
527807
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