Title :
A high-speed differential receiver with low-power interleaved direct decision feedback equalizer
Author :
Han, Min-Sik ; Yang, Sang-Hyuk ; Kim, Suki ; Lim, Shin-Il
Author_Institution :
Dept. of Electr. Eng., Korea Univ., Seoul, South Korea
Abstract :
A high-speed differential receiver with low-power interleaved direct decision feedback equalizer (DFE) is proposed and designed with a 0.18 um CMOS process. To save the power consumption, the new feedback topology is introduced. This architecture feeds back the previous bit to the proposed latch block. As a result, the adder blocks can be removed obtaining the low-power interleaved direct DFE. The current mode logic (CML) latch with embedded adder is used to reduce power consumption.
Keywords :
CMOS integrated circuits; adders; current-mode circuits; decision feedback equalisers; flip-flops; low-power electronics; CMOS process; current mode logic latch; embedded adder; high-speed differential receiver; low-power interleaved direct decision feedback equalizer; power consumption; size 0.18 mum; Adders; Bandwidth; CMOS logic circuits; CMOS process; Crosstalk; Decision feedback equalizers; Energy consumption; Interleaved codes; Intersymbol interference; Power engineering and energy; Decision feedback equalizer; differential; interleave; low power; recevier;
Conference_Titel :
SoC Design Conference (ISOCC), 2009 International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-5034-3
Electronic_ISBN :
978-1-4244-5035-0
DOI :
10.1109/SOCDC.2009.5423824
