Title :
Chip-level performance improvement using triple damascene wiring design concept for 0.13 /spl mu/m CMOS devices
Author :
Oda, N. ; Matsumoto, A. ; Yokoyama, T. ; Ishigami, T. ; Motoyama, K. ; Morita, N. ; Aizawa, K. ; Kishimoto, R. ; Gormi, H.
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
Abstract :
A novel wiring design concept called "Triple Damascene" is presented. We propose a new technology to mix wirings with different thickness in one layer by using a dual damascene process without increasing mask steps. In this technology, three types of grooves are opened simultaneously. Deep trenches for thick wires, as well as vias and shallow trenches, are selectively opened. By using this design concept, a 25% reduction in wiring delay is obtained for the critical path. A 5% reduction in chip size is also obtained as an effect of the decrease in repeater number for 0.13 /spl mu/m CMOS devices.
Keywords :
CMOS integrated circuits; delays; etching; integrated circuit interconnections; integrated circuit metallisation; 0.13 /spl mu/m CMOS devices; 0.13 mum; chip size; chip-level performance improvement; critical path; deep trenches; dual damascene process; groove opening; repeater number; shallow trenches; triple damascene wiring design concept; vias; wiring delay; CMOS technology; Delay; Etching; Laboratories; Manufacturing; Repeaters; Ultra large scale integration; Very large scale integration; Wires; Wiring;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824231
