CMOS device technology toward 50 nm region-performance and drain architecture

Author

Hori, A. ; Mizuno, B.

Author_Institution

Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

fYear

1999

Firstpage

641

Lastpage

644

Abstract

The continued scaling of Si MOSFET faces many critical issues. In this paper, the authors discuss drain architecture in relation to performance and the possibility of sub-0.1 /spl mu/m CMOS devices. It is found that an abrupt junction is indispensable for source/drain (S/D) extension to obtain higher drain current capability. On the other hand, a graded junction is desirable for deep S/D to decrease the junction capacitance. The drain architecture combined with doping technology such as plasma doping and spike anneal is one of the most important solutions for sub-0.1 /spl mu/m MOSFETs.

Keywords

CMOS integrated circuits; MOSFET; capacitance; ion implantation; plasma materials processing; rapid thermal annealing; semiconductor doping; 50 nm to 0.1 mum; CMOS device technology; Si MOSFET scaling; abrupt junction; doping technology; drain architecture; drain current capability; drive current; halo implant; junction capacitance; performance; plasma doping; reverse short channel effect; short channel effect; source/drain extension; spike anneal; sub-0.1 /spl mu/m MOSFETs; CMOS process; CMOS technology; Capacitance; Doping; Ion implantation; MOS devices; MOSFET circuits; Plasma immersion ion implantation; Technology planning; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-5410-9

Type

conf

DOI

10.1109/IEDM.1999.824234

Filename

824234