A 5.4Gbps/3.24Gbps dual-rate CDR with Strengthened up/down pulse ratio

This paper describes a clock and data recovery (CDR) circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DiaplayPort1.2 sink device. The proposed CDR uses a quarter-rate linear phase detector (PD). A charge pump is designed to compensate the different up & down pulse width of the PD and to reduce the current mismatch and power-consumption. The proposed PD strengthens the up/down pulse ratio to 5:4. The simulated peak-to-peak jitter is reduced to 7.715 ps from 25.16 ps of the conventional approach at 5.4 Gbps. A voltage-controlled oscillator (VCO) is designed for changing the operating frequency of quarter-rate clock with a ¿Mode¿ switching control. This work is designed based on 0.18 ¿m CMOS process. Simulation shows the power consumption is 117 mW from a 1.8 V supply.