Low-IF 90nm CMOS receiver for 2.5G application

In this paper, a pure digital CMOS (90nm) dual-band GSM low IF (100kHz) receiver section is presented. The incoming RF signal is first amplified using two differential LNAs (one for GSM and the other for DCS) and then down converted by two passive mixers to produce the low frequency I and Q signals. The 90 degrees phase shifted local oscillator signals are implemented on chip using two dividers by 4 and by 2 (working at 3.6GHz). The low IF strip will amplify and filter the I and Q signals. It has been built with digitally programmable gain stages including also a Butterworth 2nd order polyphase active filter. The receiver has been designed to be compatible with a standard 10-bits ADC. The RX chain shows state-of-the-art NF performances (<2dB in GSM and <3dB in DCS) with an overall current consumption of 29mA at 1.4V supply (9mA for the LNA, 17mA for the IF strip and 3mA for the divider by 2). The die area is 1.4mm×2.8mm.