A compact P+ contact resistance model for characterization of substrate coupling in modern lightly doped CMOS processes

Compact modeling of P⁺ contact resistances is important for characterization of substrate noise coupling in mixed-signal System on Chips (SoCs). Existing contact resistance models can handle uniformly doped bulk or epitaxial substrates. However, compact contact resistance models feasible for modern lightly-doped CMOS processes with P-well layers are still unavailable. This paper presents a new compact resistance model aiming at solving this problem. A Conformal Mapping (CM) method is used to derive the closed-form expressions for the resistances in the model. The model requires no fitting factors, and it is scalable to layout/substrate parameters. The proposed model can also be used to predict noise coupling in terms of S-parameters. The model validation is done by both EM simulations and measurements, and satisfactory agreement is found between the modeled and measured resistances as well as S-parameters.