Title :
An 80 nm dual-gate CMOS with shallow extensions formed after activation annealing and SALICIDE
Author :
Morifuji, E. ; Ohishi, A. ; Miyashita, K. ; Kawashima, H. ; Nakayama, T. ; Yoshimura, H. ; Toyoshima, Y.
Author_Institution :
Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan
Abstract :
Silicide compatible process flows for dual-gate CMOS with shallow extensions formed after activation annealing and Co SALICIDE (SEFAS) are proposed and adopted for 80 nm physical gate length CMOS. They show good DC and AC performances while keeping high reliability because of successful shallow extension formation. High f/sub T/ values of 80 GHz for NMOS and 47 GHz for PMOS are achieved.
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit metallisation; integrated circuit reliability; rapid thermal annealing; semiconductor device measurement; 47 GHz; 80 GHz; 80 nm; 80 nm dual-gate CMOS; AC performance; Co salicide; CoSi-SiO/sub 2/-Si; DC performance; NMOS; PMOS; SEFAS; activation annealing; cutoff frequency; gate oxide reliability; high reliability; physical gate length; ring oscillator; shallow extensions; silicide compatible process flows; Annealing; CMOS process; Electrodes; Etching; Fabrication; Hafnium; MOS devices; Oxidation; Silicides; Temperature dependence;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824236
