Direct conversion/superheterodyne W-CDMA baseband down-link channel

Author

Cusinato, Paolo

Author_Institution

Texas Instruments, Villenueve, France

Volume

1

fYear

2004

Firstpage

167

Abstract

A configurable W-CDMA baseband down-link (BDL) channel suitable to be used with both direct conversion (DIR) and superheterodyne (SHT) architectures has been integrated in a double-poly 0.6μm CMOS technology. The BDL is an analog signal processor consisting of calibrated active-RC filters and oversampled 6-bit analog-to-digital pipeline converters, which sufficiently suppresses the adjacent channel and other interferers before digital-signal processing on an external DSP. The designed BDL channel achieves 38.4dB-SNDR, 43dB-SFDR in DIR mode and 38.3dB-SNDR, 42.8dB-SFDR in SHT mode with an overall power consumption of only 49mW/58mW (DIR/SHT) from a single 2.8V power supply. A low power consumption mode allows to further reduce these values down to 41mW/50mW (DIR/SHT) without significant detrimental effects to BDL linearity performance.

Keywords

CMOS integrated circuits; RC circuits; active filters; analogue-digital conversion; code division multiple access; low-power electronics; BDL linearity; CMOS; W-CDMA; active-RC filters; adjacent channel suppression; analog signal processor; analog-to-digital pipeline converters; baseband down-link channel; digital-signal processing; direct conversion; interferer suppression; low power consumption; superheterodyne mode; Analog-digital conversion; Baseband; CMOS technology; Digital filters; Digital signal processing; Energy consumption; Multiaccess communication; Pipelines; Power supplies; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrotechnical Conference, 2004. MELECON 2004. Proceedings of the 12th IEEE Mediterranean

Print_ISBN

0-7803-8271-4

Type

conf

DOI

10.1109/MELCON.2004.1346799

Filename

1346799