• DocumentCode
    1644883
  • Title

    A 10b 1MS/s 0.5mW SAR ADC with double sampling technique

  • Author

    Lee, Tagjong ; Kim, Moo-Young ; Kim, Yongtae ; Pham, Phi-Hung

  • Author_Institution
    Dept. of Electr. Eng., Korea Univ., Seoul, South Korea
  • fYear
    2009
  • Firstpage
    512
  • Lastpage
    515
  • Abstract
    This paper introduces the 10 b 1 MS/s 0.5 mW SAR ADC with double sampling technique. It utilizes the double sampling technique to reduce power. The SAR ADC is implemented in CMOS 1P8M 65 nm technology and occupies 0.111 um2. The maximum sampling rate is 1 MS/s. The simulated SNDR and SFDR are 55.6 dB and 62.7 dB, respectively at input frequency of 484 kHz. Power consumption of the data converter is total 507 uW with 1.2-V supply.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; integrated circuit layout; CMOS technology; SAR ADC; SFDR; SNDR; analog-digital converters; double sampling technique; frequency 484 kHz; power 0.5 W; power 507 muW; size 65 nm; successive approximation register; voltage 1.2 V; Analog-digital conversion; CMOS technology; Capacitors; Circuits; Energy consumption; Energy efficiency; Frequency; Logic; Sampling methods; Voltage; 10b; 1MS/s; 1mW; ADC; SAR; data converter; double sampling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SoC Design Conference (ISOCC), 2009 International
  • Conference_Location
    Busan
  • Print_ISBN
    978-1-4244-5034-3
  • Electronic_ISBN
    978-1-4244-5035-0
  • Type

    conf

  • DOI
    10.1109/SOCDC.2009.5423831
  • Filename
    5423831
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1644883