Title :
A highly manufacturable 0.18 /spl mu/m generation logic technology
Author :
Ikeda, S. ; Yoshida, Y. ; Shoji, K. ; Kuroda, K. ; Komori, K. ; Suzuki, N. ; Okuyama, K. ; Kamohara, S. ; Ishitsuka, N. ; Miura, H. ; Murakami, E. ; Yamanaka, T.
Author_Institution :
Process Dev. Dept., Hitachi Ltd., Tokyo, Japan
Abstract :
A 0.18 /spl mu/m generation logic technology has been developed with 0.14 /spl mu/m gate length transistors. Guidelines to suppress mechanical stress in shallow trench isolation are clearly described. Stable Co salicide process has been integrated with the combination of NO treated gate oxide and BF/sub 2/ source drain ion implantation. Amorphous Si with RTA is the key to control grain size and suppress large variation of drain current in small size transistors. Two kinds of metallization systems, aluminum with SiOF dielectrics and dual damascene Cu are developed in the same layout rule.
Keywords :
MOS logic circuits; integrated circuit layout; integrated circuit metallisation; internal stresses; ion implantation; isolation technology; large scale integration; rapid thermal annealing; 0.14 micron; 0.18 micron; Al; CoSi/sub 2/; Cu; NO; RTA; Si:BF/sub 2/; dielectrics; drain current; dual damascene; gate length; grain size; layout rule; logic technology; mechanical stress; metallization systems; salicide process; shallow trench isolation; source drain ion implantation; Amorphous materials; Grain size; Guidelines; Ion implantation; Isolation technology; Logic; Manufacturing; Metallization; Size control; Stress;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824242
