Title :
IEEE: 1141.1 applied to mixed TTL-ECL and differentlal logic
Abstract :
Although IEEE 1149.1-1990 has been primarily applied as a boundary-scan (B/S) standard to transistor-transistor logic (TTL) compatible systems, the standard is logicfamily independent. This paper makes recommendations for the application of 1149.1 to both mixed family TTL-ECL modules and to differential logic signals. It compares the use of one or two output cells and one, two or three input cells and makes recommendations for the optimum application of 1149.1 to differential logic signals.
Keywords :
Cache memory; Digital systems; Guidelines; Logic circuits; Logic design; Logic testing; Pins; Power supplies; System performance; Voltage;
Conference_Titel :
Test Conference, 1992. Proceedings., International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-0760-7
DOI :
10.1109/TEST.1992.527808
