DocumentCode
1644985
Title
Novel low-latency low-power Viterbi decoder traceback memory architecture
Author
Morling, R.C.S. ; Haron, N.
Author_Institution
Appl. DSP & VLSI Res. Group, Westminster Univ., London, UK
Volume
1
fYear
2004
Firstpage
179
Abstract
In continuous-mode Viterbi decoding, the survivor path identification occurs continuously and does not wait until the complete message has been received. While this reduces the decoding latency time, there are problems determining the survivor path as the traceback starting state is unknown. The performance of 2 existing and 4 new methods of decoding on-the-fly are described and their performance analysed in terms of residual BER as a function of SNR and traceback memory length. A low-power traceback memory architecture is introduced. This is capable of performing a traceback in a single cycle, instead of the multiple read operations of a conventional memory. It can be used with any of the traceback algorithms described.
Keywords
Viterbi decoding; error statistics; integrated memory circuits; low-power electronics; SNR; Viterbi decoder; Viterbi decoding; decoding latency time reduction; low-latency decoding; low-power traceback memory architecture; multiple read operations; on-the-fly decoding; residual BER; survivor path identification; traceback memory length; traceback starting state; Data mining; Decoding; Delay; Digital signal processing; Encoding; Memory architecture; Performance analysis; Tail; Very large scale integration; Viterbi algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrotechnical Conference, 2004. MELECON 2004. Proceedings of the 12th IEEE Mediterranean
Print_ISBN
0-7803-8271-4
Type
conf
DOI
10.1109/MELCON.2004.1346802
Filename
1346802
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